The present invention relates to a semiconductor integrated circuit device including a macro cell on which three or more wiring layers is required to be formed, and its manufacturing method. Particularly, the present invention relates to a semiconductor integrated circuit device in which a plurality of macro cells whose originally necessary number of metal wiring layers differs is embedded on the same semiconductor chip, and its manufacturing method.
Moreover, the present invention relates to a large scale integrated circuit (LSI) in which an ASIC (application-specific integrated circuit) section and a semiconductor memory section are embedded, and its manufacturing method.
This application is based on Japanese Patent Application No. 9-2091, filed on Jan. 9, 1997, the contents of which is cited herein by reference. This application is based on Japanese Patent Application No. 9-2091, filed on Jan. 9, 1997, the contents of which is cited herein by reference. In recent years, in the manufacture of LSI, there is a case in which a plurality of kinds of macro cells is embedded on the same semiconductor chip. In this case, the originally necessary number of metal wiring layers, which is formed on a semiconductor substrate, differs.
For example, as shown in FIG. 1, there is a case in which an ASIC section 61 and a memory section 62 are formed in an adjacent area on an LSI chip 60. Further, as shown in FIG. 2, there is a case in which an ASIC section 61 having three wiring layers and a memory section having two wiring layers are embedded on a semiconductor substrate 70.
On the LSI chip 60, ASIC section 60 has a first wiring layer 71, a second wiring layer 72, and a third wiring layer 73. Though the memory section 62 has the first and second wiring layers, but no third wiring layer 73.
In FIG. 2, reference numeral 72a shows a first contact plug for connecting the second wiring layer 72 to the first wiring layer 71. Reference numeral 73a shows a second contact plug for connecting the third wiring layer 73 to the second wiring layer 72. Reference numeral 74 is a first insulating layer on the semiconductor substrate. Reference numeral 75 is a second insulating layer on the first wiring layer 71. Reference numeral 76 is a third insulating layer on the second wiring layer 72. Reference numeral 77 is a fourth insulating layer formed on the third wiring layer 76 of the memory section 62 and the third wiring layer 73 of the ASIC section 61.
In forming the third wiring layer 73 of the ASIC section 61 on the same chip as the memory section, a surface of the second wiring layer 72 is flattened in the conventional process as shown in FIG. 2. Due to this, a film thickness of the second wiring layer 72 is reduced, and its wiring resistance is increased. However, it is assumed that the macro cell whose number of the necessary wiring layers is small (memory cell section 62 in this example), the uppermost wiring layer (second wiring layer 72) is used as a power supply line. In this case, a potential drop, which is caused by an increase in the wiring resistance, is increased. Also, it is assumed that the uppermost wiring layer is used as a signal line, which determines an operation velocity of the memory, that is, a critical path. In this case, a wiring delay is increased by an increase in the wiring resistance. Due to this, an electrical characteristic (performance) as an LSI chip is lowered.
Thus, in the conventional LSI in which a plurality of macro cells whose originally necessary number of metal wiring layers differs is embedded on the same semiconductor chip, the film thickness of the wiring layer having a macro cell whose number of the necessary wiring layers is small is reduced, and its wiring resistance is increased. As a result, the potential drop and the wiring delay are increased by the increase in the wiring resistance.